The present disclosure relates to clock recovery during data transfer in electrical systems. Transmitted data is usually synchronised to a clock signal at a transmitter to ensure correct timing of the transmitted data and compliance with specification in terms of jitter, etc. In systems where the clock signal is transmitted alongside the data, extraction of the data is the straightforward task of examining the data signal in synchronism with the clock. In systems where the clock is not so transmitted a replica clock may be recovered from the data itself and used likewise. For example 1000BASE-X and 10GBASE-KR Ethernet are single wire pair systems in which there is no clock transmission. In many situations (typically involving high speed, long distance or significant noise) clock recovery itself is a highly non trivial task.
It is neither always nor necessarily the case but single wire pair data transmission between or within equipment is often performed by a device which receives data to be transmitted in parallel from a source, renders it into serial form and transmits it, typically at higher speed, over the single wire pair to a second receiver device which includes a clock and data recovery circuit (CDR) to recover a clock signal so that the now serial data may be extracted an expanded back out to parallel form for use at the receiver location. Typically, both devices are similar so that transmission may occur in either direction. Such devices are often referred to as SerDes devices and a typical arrangement is depicted in FIG. 1, wherein it will be noted that the receiving serdes device is shown to include CDR circuitry.
The purpose of the clock recovery circuitry may be seen as identifying two neighbouring transitions (for example by oversampling the incoming data stream and looking for two adjacent non-matching oversampled values) and placing a data sampling point mid way between them to capture a data value. This is depicted in FIG. 2.
Of course not every adjacent data pair will be subject to transition and so the clock recovery circuitry may be free running to place sample points at equivalent positions until a next transition occurs. This makes CDR vulnerable to any jitter that was present in the original clock to which the data was synchronised. Clearly if that jitter resulted in transitions that were too close (or far apart), then the sample points are likely to be consistently too early (or late).
If jitter is too great, CDR can break down completely and steps must be taken to ensure this cannot happen. To this end, for example, most transmission specifications set an upper limit on jitter with which a receiver is expected to cope.
As SerDes speeds have increased, more and more complex clock recovery circuits have become available which incorporate corrections for various anticipated errors and difficulties. Examples are discussed in United Kingdom Patent Specification GB2,473,748B and numerous others. Usually CDR is either first order, in which a next sample point is determined from current measurements, or second order in which previous corrections are taken into account: GB2,473,748B is exemplary of both.
As mentioned above, the SERDES devices which communicate between or within equipment are usually similar in nature in that they perform to similar standards and protocols. However, this may not be the case where legacy equipment is involved. New equipment may be required to perform data transfer not only with similar new equipment but also with equipment which operates according to an earlier standard. In the field of data transfer, earlier often means slower. For example, it may be desired to interface equipment designed for 10GBASE Ethernet (10 GHz clock) with equipment designed for 1000BASE Ethernet (1 GHz clock). Fortunately, this should be achievable since the specification of 10GBASE Ethernet requires that transfer speed extend down to 1 GHz. However, if it were desired to connect the same equipment to legacy equipment conforming to 100BASE-FX (100 MHz clock), the situation would be different since 100 MHz is outside the range provided for in 10GBASE. Of course, the equipments may be physically connected together without electrical incompatibility but that does not means that data transfer is possible, the basic problem is that in the upstream direction (100BASE-FX to 10GBASE) the CDR circuitry in the SerDes device is unable to reliably recover a clock from data at the slower data rate.
In the downstream direction, data transfer would be possible if each bit to be transferred from the 10 G Serdes were simply repeated 10 times at the lowest permitted clock speed, thereby making the data appear to be clocked at 100 MHz. Since these bits would be synchronised to an internal clock of the Serdes which satisfies the jitter requirements of 10GBASE internet, they should be more than accurate enough for the 100BASE Serdes and downstream data transfer should work. The only overhead would be the repeat function, which likely could be accommodated in software configuring the SERDES.
In the upstream direction, unfortunately, the same approach cannot be used straightforwardly. Although at the upstream serdes the data could be regarded as arriving with each bit repeated 10 times and thus the problem potentially solved simply by discarding 9 bits out of each 10, it is in fact unlikely that the data could be recovered at all. If the slower clock were subject to 10% jitter, that is a whole bit time at the 1 G clock speed and clearly the upstream SERDES CDR circuit could not function at all with such ambiguity as the transition boundaries are entirely overlapping. A prudent designer would expect to allow for 20% deterioration from an ideal channel due to noise, jitter and inter symbol interference, so the scale of this problem may thus be appreciated.
Clearly a hardware solution at the downstream end is required to adapt the legacy equipment such as a data resynchroniser to a tightly specified clock or in the extreme a 1000BASE serdes itself. Unfortunately such difficulty and cost may negate the reasons for retaining the legacy equipment in the first place. According the present disclosure has been made in the course of realising a different approach of using resources within a typical 10 G serdes.
According to the present disclosure there is provided apparatus and method as set forth in the claims.